1. Field of the Invention
The present invention relates generally to microelectronic structures, and more specifically to radiation-hardened microelectronic structures.
2. Description of the Background Art
Compared to other microelectronic device designs, silicon-on-insulator (SOI) structures inherently have some aspects of improved radiation hardness, such as for single-event effects. Even with this improved radiation hardness, however, SOI structures, when used in harsh total-dose environments, are still prone to radiation-induced failure due to positive charge build up in the buried oxide layer (BOX). This radiation-induced charge build-up in the BOX causes deleterious changes in the device operating parameters, such as back-channel threshold voltage and leakage current.
The prior art has, to a limited extent, mitigated this problem by implanting positively charged ions, such as boron, into the silicon substrate to raise the back-channel threshold voltage. Additional improvements in radiation hardness, however, are desirable for long term usage of SOI structures in harsh environments such as outer space, nuclear reactors, and particle accelerators. Additionally, improved radiation hardness is growing increasingly useful as semiconductor processing becomes more radiative. For example, processing techniques such as reactive ion etching and plasma etching introduce some radiation damage into the fabricated semiconductor structure.